1. Field of the Invention
Embodiments of the present invention relate to a method for manufacturing a semiconductor device. More particularly, embodiments of the present invention relate to a method for forming hard mask patterns having a reduced pitch therebetween using a double patterning process, and a method for forming a semiconductor device using the same.
2. Description of the Related Art
In general, manufacturing of highly integrated semiconductor devices may require formation of a large number of miniaturized elements, e.g., semiconductor patterns, and integration thereof within a small area. Conventional formation of semiconductor patterns, e.g., interconnect patterns, may be achieved via, e.g., photolithography and film patterning. Integration of semiconductor devices in a small area may require a reduced pitch therebetween, i.e., a reduced sum of a width of one pattern and a width of one space between adjacent patterns.
Reducing a pitch between adjacent semiconductor patterns may be limited when using a conventional photolithography process due to resolution restrictions, e.g., when forming a line and space (L/S) pattern on a substrate. Further, conventional formation of a hard mask having fine patterns with a reduced pitch therebetween may be complex and may provide uneven and/or short pattern profiles, thereby triggering potential pattern collapse and/or electrical failures.